1. Field of the Invention
The invention relates generally to video display systems, and more particularly to a method and apparatus for converting an input video signal of a first viewable display resolution, pixel rate, and line rate, to a second output video signal of a second viewable display resolution, pixel rate, and line rate.
2. Description of the Related Art
There are numerous kinds of interlaced video signals such as NTSC and PAL, as well as progressive scan video signals such as computer video output VESA VGA, SVGA, XGA, and SXGA. These and other sources typically have different resolutions in terms of pixels per line, lines per frame, as well as different video timing in terms of horizontal line rate and vertical refresh rate. In order to accommodate many different types of input video signals for viewing on a single display device several methodologies have been adopted in the prior art.
A first prior art method involves adapting the operating format of the display device to match the resolution and video timing of the source input video. According to this method, the display device must be capable of adapting to different resolutions and video timings of the available input video sources. Therefore, this prior art methodology is commonly practiced with Cathode Ray Tube (CRT) devices which display video image data by modulating an electron beam intensity while sweeping the beam both horizontally and vertically across a phosphor coated viewing surface. The CRT can adapt to different input formats by detecting the input video source horizontal line and vertical frame rate and then automatically phase locking and adjusting the CRT display horizontal and vertical sweep rates to the detected input rates in order to maximize the active portion displayed on the viewing surface.
This first prior art method is not commonly used for displays wherein the viewable display region is made up of discrete image elements (pixels) arranged in a two dimensional matrix and wherein no horizontal and vertical beam sweep apparatus is provided which can be adjusted to accommodate different input formats. One class of such discrete pixel displays is referred to as Flat Panel Displays (FPDs) which includes Liquid Crystal Displays (LCDs), Field Emissive Displays (FEDs), Plasma Display Panels (PDPs), as well as many other emerging technologies.
A second prior art method of accommodating different types of input video signals for viewing on a single display device involves converting the source resolution and timing to a format that is supported by the display device. This prior art method converts the input source video format by means of pixel conversion, line conversion, and frame frequency conversion to a target video format that is supported by the target display device. Conventional format conversion circuits operate by taking a digital video signal, extracting the desired viewable or active portion of the video fields or frames, and storing the active portion into a frame buffer. The frame buffer provides elasticity so that the data write rate need not match the display read rate. The stored data is then read from the display frame buffer and processed to convert the number of pixels per image line, and the number of lines per image, to match those of the display device.
Such processing typically incurs latency between the time when source video data is available at the video source, and the time when the resulting processed data is available for output to the display device. It has also been common practice in some systems to process the data first before storing the data in the frame buffer. In either of these prior art processing scenarios, a display timing generator is provided which operates at the desired display line and frame rate and generates synchronizing signals to control the display as well as the transfer of processed frame buffer data to the display. The display timing generator produces timing for a different number of pixels per line and line rate than the video input source in order to achieve the format conversion. Also, by operating the display timing generator at a different frame rate than the video input source frame rate, a conversion of frame rates is achieved. Conventionally, such display timing generators are either synchronized on a frame by frame basis to maintain frame lock with the input video source, or are allowed to free run relative to the input video frame rate.
When the display timing generator is free running then the rate at which video input lines are required to be processed into display output lines may not match the display output line rate, and the difference between the actual input rate and the required input rate to sustain the processed display rate must be accommodated through memory buffering. Also, if the input and output frame or field rates do not match, then input frames or fields are either repeated or dropped by the frame buffer controller. This results in temporal artifacts for high motion sequences because of repeated or dropped input frames or fields being used as source data for processing into display frames. Also, when only a single frame of memory is provided in the memory buffer and the display frame rate is not locked with the input video frame or field rate then the input video data write pointer can cross paths with the display processing data read pointer creating the situation where a display frame may be comprised of image data processed from two different input frames captured at different points in time. This produces an objectionable artifact, usually referred to as "frame tear", in the display output when the source video contains high motion sequences as media content. Thus, if the display device can lock the display frame or field rate to the input video frame or field rate there are significant advantages because fields or frames no longer need to be repeated or discarded and temporal distortions in the display video sequence can be eliminated.
In the majority of pixel based displays, such as FPD devices, the individual pixel elements are selected or enabled through the use of an orthogonal scanned interface where pixel columns are selected based on a number of timing clock cycles relative to a horizontal sync signal or data enable signal, and a particular row of pixels is selected based on the number of horizontal sync or data enable pulses that have occurred relative to a vertical sync position. This column and row selection process enables a pixel or group of pixels to be refreshed.
In the case of format conversion, it has become common practice to frame lock a display timing generator with an input video source by allowing the display timing generator to free run from the start of the display vertical sync pulse, through the entire active region, to the vertical blanking front porch region. At this point, the display timing generator continues to scan blank lines until the input video vertical sync pulse causes the display timing generator to immediately jump to the start of the display vertical sync pulse. Then, the display timing generator returns to free run operation. Many pixel based displays can accommodate this step change to the display timing sequence since the individual pixel or groups of pixel elements are addressable in a sequential fashion relative to the synchronization pulses. Once the entire active region has been updated, the step change to timing in the vertical blanking front porch region, prior to the vertical synchronization pulse, does not visually affect the display. It is relatively easy to implement a "vertical reset" feature in a display timing generator. The other advantage to this technique is that the display timing generator can use a free running display pixel clock which need not be synchronized to the input video pixel clock, line rate, or frame rate.
However, a principal disadvantage of this technique is that since the display line rate is based on a free running pixel clock, there can be no exact relationship between the input line rate and the rate at which the input lines need to be processed to sustain the display output rate. Therefore, this implementation requires that enough memory be provided so that input video lines of data are available to sustain the display processing rate for the worst case difference between the input video line rate and the display output processing line rate. Thus, in many format conversion systems a full frame buffer or more of memory is provided. Another significant disadvantage is that this type of frame locking can not be used to drive a CRT type of display device since in many cases the step change to the display timing is of sufficient magnitude to cause the horizontal and vertical sweep phase lock loops of the CRT controller to lose lock and the resulting transient during lock acquisition causes noticeable artifacts on the resulting displayed video images.
Also, for applications requiring arbitrary image zoom or shrink processing of the active pixel data as part of the format conversion capability, large amounts of memory are required. Therefore, most arbitrary zoom or shrink systems are implemented with a full frame of memory or more.
For the standard application of converting input formats to a different output format where both formats have the same aspect ratio, the required image zoom or shrink is not entirely arbitrary and the ratio of active pixels to total pixels, and active lines to total lines, tends to remain constant for most input formats of the same aspect ratio. In this situation, using a free running display timing generator requires more memory than other possible implementations, even if it has vertical reset for frame synchronization.
One example of a display processor implementation is described in U.S. Pat. No. 5,600,347 in which a method is set forth for nonlinear horizontal expansion. However, this prior art patent does not deal with the synchronization issues discussed above relating to performing format conversion with a minimum amount of memory buffer.
Many discrete pixel displays such as FPD devices have undergone technological improvements that enable them to now support a range of frame refresh rates so that frame rate conversion may not be required in the future. Nonetheless, due to the discrete pixel nature of these devices there is still a requirement for apparatus to adapt the input source video pixel rate, line rate, and displayable format to match the fixed active pixel arrangement of the display device.
Therefore, a display timing generator implementation which supports free running modes in applications where a frame buffer is used for arbitrary zoom, shrink, or other image processing, is highly desirable. Preferably, such a display timing generator should also provide a frame lock implementation that minimizes the above-discussed step change to the display timing sequence, so that both discrete pixel display devices as well as CRT devices can be supported. The novel apparatus should implement a display timing generation technique that minimizes the memory buffer needed to support non-arbitrary zoom, shrink, or image processing operations for format conversions. As indicated above, such a display timing generator is highly desirable since it would reduce the costs of video processing systems and provide a common apparatus that could be utilized in many types of devices for converting images from a first input format to a second display format.
The following patents provide descriptions of the various prior art systems discussed above:
U.S. Pat. No. 4,275,421 entitled LCD CONTROLLER; PA1 U.S. Pat. No. 4,872,054 entitled VIDEO INTERFACE FOR CAPTURING AN INCOMING SIGNAL AND REFORMATTING THE VIDEO SIGNAL; PA1 U.S. Pat. No. 5,351,088 entitled IMAGE DISPLAY APPARATUS FOR DISPLAYING IMAGES OF A PLURALITY OF KINDS OF VIDEO SIGNALS WITH ASYNCHRONOUS SYNCHRONIZING SIGNALS AND A TIMING CORRECTION CIRCUIT; PA1 U.S. Pat. No. 5,446,496 entitled FRAME RATE CONVERSION WITH ASYNCHRONOUS PIXEL CLOCKS; PA1 U.S. Pat. No. 5,508,714 entitled DISPLAY CONTROL APPARATUS FOR CONVERTING CRT RESOLUTION INTO PDP RESOLUTION BY HARDWARE; PA1 U.S. Pat. No. 5,517,253 entitled MULTI-SOURCE VIDEO SYNCHRONIZATION; PA1 U.S. Pat. No. 5,534,883 entitled VIDEO SIGNAL INTERFACE; PA1 U.S. Pat. No. 5,561,472 entitled VIDEO CONVERTER HAVING RELOCATABLE AND RESIZABLE WINDOWS; PA1 U.S. Pat. No. 5,579,025 entitled DISPLAY CONTROL DEVICE FOR CONTROLLING FIRST AND SECOND DISPLAYS OF DIFFERENT TYPES; PA1 U.S. Pat. No. 5,600,347 entitled HORIZONTAL IMAGE EXPANSION SYSTEM FOR FLAT PANEL DISPLAYS; and PA1 U.S. Pat. No. 5,585,856 entitled IMAGE PROCESSING APPARATUS THAT CAN PROVIDE IMAGE DATA OF HIGH QUALITY WITHOUT DETERIORATION IN PICTURE QUALITY. PA1 programming interface means for receiving operating mode information indicative of said first and second viewable display resolutions, pixel rates and line rates; PA1 memory means for storing said digital video input signal; PA1 display processor means for retrieving said digital video input signal from said memory means, selectively de-interlacing, filtering and scaling said digital video input signal, and in response generating said digital video output signal; and PA1 display timing controller means for deriving synchronization and control information from said digital video input signal based on said operating mode information received by said programming interface means, and in response controlling operation of said display processor means to generate said digital video output signal for display at said second viewable display resolution, pixel rate and line rate. PA1 clock generation means for generating a display main clock signal; PA1 a lock event controller for generating a lock event signal at a predetermined instant of each frame of said digital video input signal; display synchronizer means for generating a display horizontal lock event signal and a display vertical lock event signal for controlling synchronization between said digital video input signal and said digital video output signal based on said lock event signal and said operating mode information; and PA1 display timing generator means for generating timing signals synchronized to said horizontal and vertical lock event signals to control said display processor means in accordance with said operating mode information.